CoreSight: Initial steps in supporting HW assisted tracing on Linux for ARM SoCs
One of the challenges when developing products based on ARM SoC (System on Chip) solutions is debugging the complex interactions of a software stack that runs across multiple HW components (GPU, CPU, DSPs, etc). To help alleviate the complexity introduced by the interconnection of those components, a wealth of debugging tools and hardware assisted tracing solutions are available, largely falling under the ARM® CoreSight™ technology.
In this post concentrate on hardware assisted tracing (simply referred to as CoreSight from hereon) where IP blocks are added to a design based on the components found in the SoC and expected tracing needs, providing an on-system solution that is flexible and easily adaptable. The blocks themselves are inter-connected and categorized as data sources, links and sinks, each being enabled and configured at run time based on specific scenarios. A typical CoreSight system is represented in the below diagram (source: ARM Ltd):
Current support in the Linux kernel for hardware-assisted tracing on ARM SoCs with CoreSight technology is fairly limited. Today’s solutions are generally static, tailored to a single architecture, hardly extensible and not maintained. The result is a fragmented landscape of proprietary solutions targeting very specific goals. These solutions are by their nature not fit for upstream acceptance. In user space, the situation is just as difficult since there is no tool available to collect and package the configuration data, let alone decode the compressed streams
Over the last several months Linaro has been working hard on Coresight support in the Linux kernel. Starting from the initial submission from codeAurora back in December of 2012, we addressed all comments that came back from the community. Two more rounds (V1 and V2) were then posted for review, each time making modifications to provide a more generic solution that is more suitable for integration into the Linux kernel. A third set, to be released in the coming days, allows multiple sinks to be enabled simultaneously, whether they belong to the same Coresight source or not. This feature marks a sharp improvement over the initial implementation, increasing the debugging capabilities of the solution.
Despite being satisfied with the ongoing upstreaming process, the CoreSight team at Linaro (and the community at large) is still faced with serious challenges, most notably in the area of packaging source configuration information (commonly called “metadata”) and decoding trace streams generated by trace sources. Although we haven’t identified any generic solutions, significant progress on trace decoding has been achieved lately. Working in partnership with our friends at ARM Ltd, trace streams generated on the TC2 platforms have been decoded. The process, documented here and available to all, can seem convoluted at first, but steps are explained thoroughly and example files provided so that interested parties can start from a working example. Last but not least, we have started to look at how support for STMs (System Trace Macrocells) can be integrated to the existing CoreSight framework and how it can be utilised in conjunction with existing kernel subsystems, most notably in the area of debugging. The main challenge will be to find a way to define and configure channels between kernel and user space, something we intend to take to the community by hosting a talk at the Linux Plumbers Conference in Dusseldorf (Germany) in October.
ARM® CoreSight™ is an ARM trademark.